Plating metals by electroplating or electroless plating over a seed layer on a wafer is a common process in the manufacture of semiconductor devices. Requirements for plating processes in semiconductor device manufacturing have become increasingly stringent as device features become smaller and wafer sizes become larger.
One such property is uniform plating across the wafer surface. Another desirable property is to uniformly fill device features (such as vias and trenches) such that no voids exist in the features and the surface of the plated metal is globally planar. Yet another property is to plate metal without damaging the plated metal or any underlying layer. Still another property is for the plating process to be cost effective.
Electro-plating typically involves a rotating wafer with a thin seed layer and an electrolytic bath. Electric potential is applied between an anode and a cathodic wafer, both in contact with the electrolytic bath. Cathodic contact with the wafer may be established using electrical contacts at the wafer edge. Electrolyte flow may be maintained to improve electrolyte transfer to the wafer surface. The applied electric potential drives a current between the anode and cathode, and the metal to be plated is deposited on the wafer.
Electroplating processes known in the art are deficient in several ways. First, thin seed layers tend to be resistive and result in a potential drop between the wafer edge where electrode contact has been established and the wafer center where there is no direct electrode contact. The potential drop causes variations in current density across the wafer surface, which may contribute to poor plating uniformity. The variations are more noticeable as the wafer size increases and the seed layer becomes thinner (which is a prevalent trend in the semiconductor industry). Secondly, features with small dimensional sizes and/or high aspect ratios are often plated with voids in the features and residual topography on the plated metal surface. This is particularly so when the feature size is below 0.18 μm with an aspect ratio greater than 4 to 1. Thirdly, a large amount of metal may need to be plated for the plating process to be integrated with subsequent processes such as polishing. Since large amounts of metal are first plated and subsequently polished away, the plating and polishing processes represented as an integrated module may be inefficient and costly.
Current density variation across the wafer surface may be reduced by various techniques to improve plating uniformity. One such technique utilizes a porous compressible member which has a conductive surface covering a rotating wafer surface. The porous compressible member, commonly called a sponge, covers a large portion of the surface being plated and distributes current across the surface. Materials used to form the conductive surface on the sponge are metal fillers or conducting polymers such as polyaniline. However, metal fillers may damage the wafer surface as the wafer rotates with respect to the sponge, thereby resulting in poor device yields. Furthermore, conducting polymers, such as polyaniline, lack the structural integrity to withstand the stress caused by rotating the wafer with respect to the sponge.
Another technique utilizes conductive electrical contacts that are formed by pushing conductive wires, pins, brushes or spherical balls against a wafer surface. Several such contacts are utilized to distribute current across the wafer surface. However, pushing such contacts against the wafer surface may damage the plated metal and underlying layers, particularly due to sliding friction when the wafer is rotated with respect to the contacts. Furthermore, such wafer surface damage may result in poor device yields. In some instances, a thin electrolyte layer may be applied between the wafer surface and the electrical contact to reduce the damage. However, the electrolyte layer is conductive and provides a direct path of current flow between the electrical contacts and the anode that may result in poor power and plating efficiency.
Void formation and topography may be reduced by various techniques utilizing a sequence of plating and polishing processes. One such technique is pulse plating. Periodic reversal of the plating voltage electro-polishes a portion of the metal previously plated. Polishing is faster at regions that are higher than surrounding regions on the wafer surface and at regions that have narrower features, where electric currents are higher in magnitude. This technique reduces void formation and local topography within specific regions of the semiconductor device, but generally does not benefit topography globally across the semiconductor device.
Another technique is first plating a wafer and then applying a mask to low regions of the wafer during an electro-polishing process. Polishing occurs in high regions that are not masked, increasing planarity of the semiconductor device. However, this technique generally requires two discrete processes and is costly to implement. Another disadvantage of this technique is that the masks utilized are often degraded by the electrolyte itself and may result in poor planarity.
Yet another technique utilizes a bipolar electrode to intermittently plate and polish a wafer surface. The bipolar electrode is arranged so as to facilitate the flow of current from an anode through a portion of an electrolytic solution, through the wafer surface, into another portion of the electrolytic solution, and then into a cathode. Plating occurs in the portion of the wafer surface exposed to the anode and polishing occurs in the portion of the wafer surface exposed to the cathode. Simultaneous plating and polishing occurs to yield a planar surface. However, the polishing action is primarily an electropolishing action and is isotropic such that the resulting surface of the plated metal is locally planar but has poor global planarity. Another disadvantage of this technique is that for plating to be practical, the net plating action may need to be substantially larger than the net polishing action, usually by arranging the bipolar electrode and wafer such that the portion of the wafer surface being plated is substantially larger than the portion being polished. Since the net current flow between the anode and cathode is fixed, this arrangement may lead to current density differences between the two portions of the wafer surface and uneven plating across the wafer surface. Still another disadvantage of this technique is that it increases the path through which current flows from the anode to the cathode. Thus, the capacitance and resistance of the current path is increased making it less responsive to fluctuating currents, such as in pulse plating, and may result in poorly filled features on the wafer surface.
Still another technique involves intermittently applying a polishing force between a pad and the wafer surface during the plating process. Plating and polishing processes occur in different chambers separated by a partition. Polishing occurs in the regions where the polishing action is applied and a globally planar surface is obtained. However, cross-contamination often occurs between the polishing and plating chambers, degrading the quality of the plated metal. Generally, the use of multiple chambers increases complexity of the apparatus resulting in higher costs. Yet another disadvantage of this technique is that obtaining sufficient planarity often requires use of hard pads pushed against the substrate surface with a high force, damaging the plated metal and underlying layers.
Another method for plating metals on a substrate is electroless plating (also called electroless deposition) that involves a wafer immersed in an electroless bath. The wafer surface is typically activated to make it catalytic in nature. The catalyzed surface reacts with the electroless bath to form a metal layer on the wafer surface. Small quantities of the electroless metal itself also acts as a catalyst, so the deposition is autocatalytic once a thin layer of metal has been formed on the original wafer surface. Unlike electro-plating, electroless plating is a completely chemical process and does not require electrode placement for material deposition. Accordingly, an apparatus for electroless plating are simpler and usually less costly compared to an electro-plating device. Another significant benefit of the electroless process is that it may be used to deposit a metal layer on a non-conducting surface. However, electroless plating rates are significantly slower compared to electro-plating and commercially less viable for many applications. Another disadvantage of electroless plating is that it is a conformal deposition process and suffers from the planarization related disadvantages described above.
Sequential plating and mechanical polishing techniques to form planar surfaces generally require an anode and a cathode for successful plating (as is commonly done in electro-plating systems). These techniques cannot be applied to electroless plating since electroless plating tools do not use anode and/or cathode electrodes. Intermittently applying a pad to the wafer surface during electroless plating may improve planarization, but further reduces effective plating rate of the metal and impacts commercial viability. Therefore, planarization in electroless plated surfaces still pose disadvantages. In addition, electroless plating baths often use environmentally hazardous materials (such as formaldehyde, a known carcinogen) significantly limiting their use in commercial applications. Yet another disadvantage of electroless plating is that since it does not depend on electric currents, it may be a difficult process to regulate.
Accordingly, there is a need for a plating method and apparatus that addresses some or all of the drawbacks of prior art plating techniques.